1. Field of the Invention
The present invention relates to a CCD (charge coupled device) image sensor, more particularly, to a CCD image sensor adapted to resolution switching.
2. Description of the Related Art
Multi-function printers (MFP), which are complex machines having functions of an image scanner, a facsimile, a printer and so on, have become popular due to the technical advancement in recent years. In multi-function printers, the following two types of sensors have been put into practical use: an CCD image sensor adapted to optical image reduction with an optical lens; and a contact image sensor (CIS) comprising a contact rod lens and a color cell guide having a built-in LED emitting device, which is more cost-effective.
Various types of contact image sensors are known in the art. One example is a CMOS image senor array in which a plurality of CMOS image sensor chips are arranged and another example is a CCD image sensor array in which a plurality of CCD image sensors are arranged as disclosed in Japanese Laid-Open Patent Application No. JP-A Heisei 11-234473.
FIG. 1 is a block diagram illustrating the configuration of a prototype image sensor array provided with a pair of CCD image sensors, which has been developed by the inventor. The image sensor array shown in FIG. 1 is provided with first and second CCD image sensors 101 and 102, a timing generator 103, and a switch circuit 111.
The first and second CCD image sensors 101 and 102 are each provided with: a plurality of photodiodes for photoelectric conversion; memories temporarily holding electric charges received from the photodiodes; and a CCD shift register transferring the electric charges received from the memories to the output terminal. A first transfer gate is provided between the photodiodes and the memories, and a second transfer gate is provided between the memories and the CCD shift register.
The timing generator 103 has a function of supplying control signals (which may be referred to as clock pulses, hereinafter) required for driving these CCD image sensors. The timing generator 103 is connected to the first and second CCD image sensors 101 and 102, and supplies a first transfer gate signal ΦTG100 to the first and second CCD image sensors 101 and 102. The timing generator 103 also feeds control signals (referred to as the first CCD control signals 116, hereinafter) to the first CCD image sensor 101, including a first CCD second transfer gate signal ΦTG101, a first CCD non-inverted clock Φ101, a first CCD inverted clock Φ101B, a first CCD last gate pulse Φ101L, and a first CCD reset gate pulse Φ101R. In addition, the timing generator 103 feeds control signals (referred to as the second CCD control signals 117, hereinafter) to the second CCD image sensor 102, including a second CCD second transfer gate signal ΦTG102, a second CCD non-inverted clock Φ102, a second CCD inverted clock Φ102B, a second CCD last gate pulse Φ102L, and a second CCD reset gate pulse Φ102R.
The first transfer gate signal ΦTG100 is applied to the first transfer gates within the first and second CCD image sensors 101 and 102 to activate the first transfer gates at desired timings. The first CCD second transfer gate signal ΦTG101 is applied to the second transfer gate of the first CCD image sensor 101. The first CCD non-inverted clock Φ101 and the first CCD inverted clock Φ101B are applied to the CCD shift register of the first CCD image sensor 101. The first CCD last gate pulse Φ101L is applied to the final stage of the electric charge transfer channel of the first CCD image sensor 101. The first CCD reset gate pulse Φ101R is applied to a reset gate of the electric charge transfer channel of the first CCD image sensor 101. The second CCD second transfer gate signal ΦTG102 is applied to a second transfer gate of the second CCD image sensor 102. The second CCD non-inverted clock Φ102 and the second CCD inverted clock Φ102B are applied to an electric charge transfer channel of the second CCD image sensor 102. The second CCD last gate pulse Φ102L is applied to the final stage of the electric charge transfer channel of the second CCD image sensor 102. The second CCD reset gate pulse Φ102R is applied to a reset gate of the electric charge transfer part of the second CCD image sensor 102.
The first and second CCD control signals 116 and 117 are generated by the timing generator 103 and supplied to the first and second CCD image sensors 101 and 102, so that the output voltage signals of the first and second CCD image sensors 101 and 102 (which may be referred to as the first and second CCD output voltages VOUT101, and VOUT102, respectively) do not overlap each other in the time domain.
The switch circuit 111 has a function of selecting the output voltage signals supplied from the first and second CCD image sensors 101 and 102. The switch circuit 111 is connected to the first and second CCD image sensors 101 and 102. The switch circuit 111 is responsive to first and second switch timing control signals SW101 and SW102 received from the timing generator 103 for selecting one of the output signals from the first and second CCD image sensors 101 and 102. The selected output signal is outputted from the switch circuit 111 as a final output voltage 112.
FIG. 2 is a timing chart illustrating operation timings of the first and second CCD image sensors 101 and 102. The first and second CCD image sensors 101 and 102 have the same configuration, and the operation of the first CCD image sensor 101 is same as the operation of the second CCD image sensor 102. Therefore, a description is given in the following only of the first CCL image sensor 101.
FIG. 2 shows the waveforms of the first transfer gate signal ΦTG100, the first CCD second transfer gate signal ΦTG101, the first CCD non-inverted clock Φ101, the first CCD inverted clock Φ101B, the first CCD last gate pulse Φ101L, the first CCD reset gate pulse Φ101R, and the first CCD output voltage VOUT101.
When externally receiving a light signal, the first CCD image sensor 101 provides photoelectric conversion by using PN junctions within the photodiodes of the first CCD image sensor 101 to thereby generate electric charge signals. At the time t01 when the accumulation of the electric charge signals is completed for one line, the first transfer gate signal ΦTG100 is pulled up to the high level to turn on the first transfer gate within the first CCD image sensor 101. At this time, electric charges are transferred from the photodiodes to the memory within the first CCD image sensor 101. At the time t02, the first transfer gate signal ΦTG100 is then pulled down to the low level to turn off the first transfer gate.
This is followed by switching the first CCD second transfer gate signal ΦTG101 from the low level to the high level at the time t03, allowing the electric charges accumulated in the respective memories of the first CCD image sensor 101 are transferred to the CCD shift register connected to the memories at the reading timings of the CCD image sensors.
At the time t04, the first CCD second transfer gate signal ΦTG101 is switched from the high level to the low level to complete the transfer of the electric charges from the memories to the CCD shift register. The CCD shift register is provided with electrodes which receives the first CCD non-inverted clock Φ101 and the first CCD inverted clock Φ101B, respectively. The first CCD non-inverted clock Φ101 and the first CCD inverted clock Φ101B are set to the high level and the low-level, respectively, and thereby the electric charges transferred to the CCD shift register are sequentially transferred to the last gate.
The first CCD last gate pulse Φ101L is fed to the last gate. At the time t05, the first CCD last gate pulse Φ101L is switched from the high level to the low level to allow the electric charges to be injected into a CFJ (Capacitor Floating Junction) provided at the subsequent stage of the last gate. The CFJ has a function of converting an electric charge signal into a voltage signal with a capacitive element. The accumulated electric charges are converted into the first CCD output voltage VOUT101, by the CFJ, and the first CCD output voltage VOUT101 is signal-amplified by an amplifier connected to the output of the CFJ.
A reset gate transistor is connected to the CFJ for initialization of the electric charges accumulated across the CFJ. The first CCD reset gate pulse Φ101R is fed to the gate terminal of the reset gate transistor. When the first CCD reset gate pulse Φ101R is switched from the low level to the high level, a VRD voltage of a predetermined voltage level (for example, 10V) is applied to the gate terminal to clear off the electric charges across the CFJ.
In the following, a description is given of the operation of the image sensor array, which incorporates the first and second CCD image sensors 101 and 102. FIG. 3 is a timing chart showing the operation of the image sensor array of FIG. 1. It should be noted that the first CCD control signals 116, including the first CCD second transfer gate signal ΦTG101, the first CCD non-inverted clock Φ101, the first CCD inverted clock Φ101B, the first CCD last gate pulse Φ101L, and the first CCD reset gate pulse Φ101R, are fed to the first CCD image sensor 101, while the second CCD control signals 117, including the second CCD second transfer gate signal (ΦTG102, the second CCD non-inverted clock Φ102, the second CCD inverted clock Φ102B, the second CCD last gate pulse Φ102L, and the second CCD reset gate pulse Φ102R, are fed to the second CCD image sensor 102.
The basic operation of the first and second CCD image sensors 101 and 102 is as described above. After the first and second CCD image sensors 101 and 102 receive light for a certain period of time, electric charges are accumulated across the photodiodes integrated therein. At the time t11, the first transfer gate signal ΦTG100 which is fed to both of the first and second CCD image sensors 101 and 102, is pulled up to the high level to thereby turn on the first transfer gates within the first and second CCD image sensors 101 and 102, simultaneously. As a result, the electric charges are transferred to the memories within each CCD image sensor in the period between the time t11 and the time t12.
This is followed by pulling up the first CCD second transfer gate signal ΦTG101 to the high level at the time t13, in order to output the electric charges accumulated in the memories of the first CCD image sensor 101 in first. The pull-up of the first CCD second transfer gate signal ΦTG101 allows the electric charges accumulated in the memories to be transferred to the CCD shift register in the first CCD image sensor 101.
At the time t14, the first switch timing control signal SW101 is switched to the high level to allow the switch circuit 111 to select the output of the first CCD image sensor 101, in order to output the pixel signal of the first CCD image sensor 101 in first. Thereafter, the first CCD control signals 116 are supplied to operate the first CCD image sensor 101, so that pixel signals are sequentially supplied from the first CCD image sensor 101 to the switch circuit 111. The switch circuit 111 outputs the final output voltage 112 in accordance with the pixel signals.
Next, the second CCD second transfer gate signal ΦTG102 is pulled up to the high level at time t15. The pull-up of the second CCD second transfer gate signal ΦTG102 allows the electric charges accumulated in the memories of the second CCD image sensor 102 to be transferred to the CCD shift register of the second CCD image sensor 102. At the time t16, the second switch timing control signal SW102 is then pulled up to the high level to allow reading the pixel signal of the second CCD image sensor 102, and the first switch timing control signal SW101 is pulled down to the low level. This allows the switch circuit 111 to select the pixel signals received from the second CCD image sensor 102. Thereafter, the second CCD control signals 117 are fed to operate the second CCD image sensor 102 so that the pixel signals are sequentially supplied from the second CCD image sensor 102 to the switch circuit 111. The switch circuit 111 outputs the final output voltage 112 in accordance with the pixel signals from the second CCD image sensor 102.
The image sensor array shown in FIG. 1 operates as thus described, outputting the pixel signals from the photodiodes integrated within the CCD image sensors.
CCD image sensors are often adapted to resolution switching. Typically, such a CCD image sensor is designed to operate in a low resolution mode in addition to the normal operation mode. In the following, an exemplary operation of the CCD image sensor for the low resolution mode will be described. Specifically, a description is given of a case when pixel signals from two pixels are added together to generate a resultant output signal in a read operation. Such operation may be also referred to as the multiple-pixel addition mode or referred to as the two-pixel addition mode for indicating that the number of relevant pixels is two. The person skilled in the art would recognize that the operation of the two-pixel addition mode results in the reduction in the resolution of the image sensor array down to half of the original resolution.
FIG. 4 is a timing chart showing operation timings of the first and second CCD image sensors 101 and 102 in the low resolution mode. As described above, the configuration and operation of the first and second CCD image sensors 101 and 102 are same. Therefore, the following description will be directed to the operation of the first CCD image sensor 101 in the low resolution mode.
FIG. 4 shows waveforms of the first transfer gate signal ΦTG100, the first CCD second transfer gate signal ΦTG101, the first CCD non-inverted clock Φ101, the first CCD inverted clock Φ101B the first CCD last gate pulse Φ101L, the first CCD reset gate pulse Φ101R. FIG. 4 also shows the amount of electric charges injected into the CFJ.
From the time t21 to t24, the operation in the two-pixel addition mode is same as the operation shown in FIG. 2. As shown in FIG. 4, cycle periods of the first CCD last gate pulse Φ101L and the first CCD reset gate pulse Φ101R are half of those of the first CCD non-inverted clock Φ101 and the first CCD inverted clock Φ101B. In this operation, electric charges of the two adjacent pixels are added together at the last gate. When a series of four photodiodes are used as first to fourth pixels of the CCD image sensor 101, for example, the electric charges of the first and second pixels, which are positioned adjacent to each other, are added together at the last gate, and the electric charges of the third and fourth pixels are added together at the last gate.
At the time t24, the second transfer gate signal ΦTG 101 is switched from the high level to the low level. At the time t25, the first CCD non-inverted clock Φ101 is switched from the high level to the low level, and this allows the electric charges generated within the first pixel to be transferred from the CCD shift register to the last gate. At the time t25, the electric charges of the first pixel are accumulated at the last gate without being transferred to the CFJ, since the first CCD last gate pulse Φ101L is set to the high level. The first CCD non-inverted clock Φ101 is switched from the low level to the high level after the time t25, and then switched from the high level to the low level at the time t26. Similarly, the first CCD inverted clock Φ101B is switched from the high level to the low level after the time t25, and switched from the low level to the high level at the time t26.
At the time t26, the electric charges generated within the second pixel are transferred from the CCD shift register and to the last gate. This allows the electric charges of the first and second pixels to be added together at the last gate. Moreover, at the time t26, the first CCD last gate pulse Φ101L is switched from the high level to the low level to transfer the electric charges of the first and second pixels accumulated at the last gate to the CFJ. The electric charges obtained by adding together the electric charges of the first and second pixels are converted into a signal voltage by the CFJ, and the resultant signal voltage is outputted from the CFJ.
This is followed by pulling up the first CCD reset gate pulse Φ101R to the high level at the time t27 to initialize the CFJ. The first CCD last gate pulse Φ101L is also pulled up to the high level at the time t27.
Similar operation is then implemented for the third and fourth pixels. The first CCD last gate pulse Φ101L is kept at the high level from the time t27 to t29. In the meantime, the first CCD non-inverted clock Φ101 is switched from the low level to the high level and then to the low level. Similarly, the first CCD inverted clock Φ101B is switched from the high level to the low level and then to the high level. At the time t28, the electric charges generated within the third pixel are transferred to the last gate through the CCD shift register. Subsequently, the first CCD non-inverted clock Φ101 is switched from the low level to the high level and then to the low level, while the first CCD inverted clock Φ101B is switched from the high level to the low level and then to the high level. At the time t29, the electric charges generated within the fourth pixel is transferred to the last gate.
At the time t29, the first CCD non-inverted clock Φ101 is switched from the high level to the low level, and the first CCD last gate pulse Φ101L is switched from the high level to the low level. This results in that the electric charges of the third and fourth pixels are added together at the last gate, and the electric charges accumulated at the last gate are transferred to the CFJ. This completes the output of the pixel signals associated with the electric charges from the photodiodes within the CCD image sensor.
Hereinafter, a description is given of the overall operation of the image sensor array provided with the first and second CCD image sensors 101 and 102, when the image sensor array is placed into the two-pixel addition mode, which results in the reduction of the resolution down to one half.
FIG. 5 is a timing chart showing the operation of the image sensor array in the two-pixel addition mode. It should be noted that the first CCD control signals 116, including the first CCD second transfer gate signal ΦT101, the first CCD non-inverted clock Φ101, the first CCD inverted clock Φ101B, the first CCD last gate pulse ΦT101L, and the first CCD reset gate pulse Φ101R, are fed to the first CCD image sensor 101, while the second CCD control signals 117, including the second CCD second transfer gate signal ΦTG102, the second CCD non-inverted clock Φ102, the second CCD inverted clock Φ102B, the second CCD last gate pulse Φ102L, and the second CCD reset gate pulse Φ102R, are fed to the second CCD image sensor 102. The basic operation of the first and second CCD image sensors 101 and 102 is same as the operation described referring to FIG. 4.
At the time t31, the first switch timing control signal SW101 is switched to the high level to select the output of the first CCD image sensor 101. This allows outputting the pixel signals of the first CCD image sensor 101 in first. In the meantime, electric charges generated within the photodiodes are transferred to the memories before the time t32 within each of the CCD image sensors 101 and 102.
The electric charges accumulated in the memories are transferred to the CCD shift register within the first CCD image sensor 101 in response to the first CCD second transfer gate signal ΦTG101. The first CCD control signals 116 are fed to the first CCD image sensor 101 so as to operate the first CCD image sensor 101 in the two-pixel addition mode (in which the resolution is reduced to one half), and signal voltages are sequentially outputted from the first CCD image sensor 101 with the electric charges of two adjacent pixels added together.
This is followed by pulling up the second switch timing control signal SW102 to the high level to select the second CCD image sensor 102, while the first switch timing control signal SW101 is pulled down to the low level This allows outputting the pixel signals of the second CCD image sensor 102 from the switch circuit 111. Before that, the second CCD second transfer gate signal ΦTG102 is switched to the high level to transfer the electric charges from the memories to the CCD shift register within the second CCD image sensor 102.
Thereafter, the second CCD control signals 117 are fed to the second CCD image sensor 102 so that the second CCD image sensor 102 operates in the two-pixel addition mode (in which the resolution is reduced to one half), and signal voltages are sequentially outputted from the second CCD image sensor 102 with the electric charges of two adjacent pixels added together.
One requirement of a CCD image sensor array is the reduction of the image reading time. The inventor has discovered that there is a room for reducing the image reading time in operating the image sensor array in the low resolution mode. In the above-described operation of the prototype CCD image sensor array, the image reading time in reading pixel signals with a normal resolution (or a high resolution) is same as that in reading pixel signals with a low resolution (or a multiple-pixel addition mode). The reading speed or charge transfer speed of a CCD image sensor is determined by the speed of transferring electric charges over the CCD shift register. Therefore, the CCD image sensor array suffers from a difficulty in enhancing the image reading speed over the maximum transfer speed of the CCD shift register, even when the image sensor array is operated in a multiple-pixel addition mode with a low resolution), This may result in that the user feels that the reading speed is slow when the image sensor array is placed into the multiple-pixel addition mode (with a low resolution). This is a problem to be avoided for both a customer who uses a scanner and a company which manufactures the scanner by using a contact image sensor device.
One may consider that the image reading time is sufficiently short when an image scanner is operated in a preview mode or the like; however, the reduction of the image reading time in a preview mode is actually achieved by omission of reading pixel signals for some pixels. The omission of reading pixel signals for some pixels allows reducing the image data conversion time and the image data transfer time. Further, the read operation from the pixels in the sub-scanning direction is not done for all of the lines of the CCD image sensor; the read operation is only performed for every multiple lines.
One potential approach to solve this problem may be to increase the charge transfer speed of the CCD shift register. For example, Japanese Laid-Open Patent Application No. JP-A Heisei 11-308409 discloses that the cycle period of the charge transfer clock is increased up to double of the normal operation mode, when the CCD image sensor chip is operated with a half resolution mode. However, the skilled person would appreciate the technical difficulty in increasing the charge transfer speed. The maximum charge transfer speed of the CCD shift register is determined by the voltage waveform of the non-inverted clock and the inverted clock supplied to the CCD shift register and by the dose amount of ions injected into the CCD shift register. Typically, signal levels of the non-inverted and inverted clocks fed to the CCD shift register are fixed to 5V or 3.3V. The signal levels of the non-inverted and inverted clocks determine the maximum operation speed and transferable electric charge amount of the CCD shift register.
One potential approach for enhancing the operation speed of the CCD shift register is to shallow the potential of the CCD shift register by reducing the dose amount of ions injected into the CCD shift register. However, the reliable operation of the CCD shift register requires a certain amount of electric charges enough to develop a pixel signal with a voltage level of 1 to 2V or more. Therefore, it is not preferable to excessively reduce the dose amount of ions injected into the CCD shift register. Another potential approach may be to shallow the potential of the CCD shift register with the width thereof increased in order to increase the volume of electric charges stored in the CCD shift register. However, this approach undesirably increases the chip size, causing the cost increase of the CCD image sensors.